Multi-layer dielectric and method of forming same

ABSTRACT

A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention is directed, generally, to an assemblyhaving a multi-layer dielectric and its method of manufacture.

[0003] 2.Description of the Prior Art

[0004] Dielectric layers are very important in the production ofintegrated circuits because they provide an insulating barrier betweenconductive layers and protect the underlying layers from such things asimpurities, moisture, and stress related impacts. It is desirable thatthe dielectric layer fill the spaces between the parallel conductors.Otherwise, voids left between the conductors can cause the circuit tofail for a variety of reasons, such as latent defects caused byimpurities and moisture. Voids between the parallel conductors can alsocause the circuits to fail due to electric shorts between structuresformed subsequent to the dielectric deposition. Furthermore, certaindielectric characteristics cause undesirable effects, such as “crosstalk” between parallel conductors of current. Accordingly, the qualityof the dielectric layer is a factor in the reliability and performanceof the integrated circuit.

[0005]FIG. 9 illustrates a dielectric formation problem known in the artknown as “shadowing”, wherein some areas in the openings 118 between thestructures 112 are more prone to developing voids 110 during theformation of the dielectric layer 102, thereby resulting in a lesseffective integrated circuit. Various attempts have been made to reduceor eliminate shadowing, and thereby improve the overall quality of thedielectric layer.

[0006] It is known to form multiple dielectric layers to providebenefits not available with a single dielectric layer to improvedielectric quality. However, several deficiencies exist in the priorart. For example, it is known to form a multi-layer dielectric having anadhesive coating between each dielectric layer. The adhesive coating,however, introduces an additional step in the fabrication process, whichreduces manufacturing efficiency and increases costs. Also, it is knownto form three layers of dielectric material having varying degrees ofquality and thickness, with the third top layer being relatively thick.Formation of a three layered dielectric, however, requires significantmanufacturing time and cost, particularly when thickness and highquality are necessary characteristics of one of the layers.

[0007] Accordingly, the need exists for an improved multiple layerdielectric providing good gap-fill characteristics, whereby only twolayers are needed, and an adhesive layer is not needed.

BRIEF SUMMARY OF THE INVENTION

[0008] The present invention is directed to an assembly having asubstrate, an opening relative to the substrate, the opening having anaspect ratio greater than about two, a first dielectric layer in theopening wherein a portion of the opening not filled with the firstdielectric layer has an aspect ratio of not greater than about two, anda second dielectric layer over the first dielectric layer. Reducing theaspect ratio of the opening by forming the first dielectric layer andcompleting the dielectric layer by forming the second dielectric layermay be achieved through changes in process settings, such astemperature, reactor chamber pressure, dopant concentration, flow rate,and spacing between the shower head and the assembly.

[0009] The present invention also includes a method of forming adielectric layer in an opening having an aspect ratio of greater thanabout two comprising forming a first dielectric layer in the openingwherein a portion of the opening not filled with the first dielectriclayer has an aspect ratio of not greater than two, and forming a seconddielectric layer over the first dielectric layer.

[0010] The present invention also may be embodied in and used to formdielectrics associated with structures such as electrical conductors inintegrated circuits, such as are used to form memory arrays, logiccircuits, memory devices, processors, and systems.

[0011] The present invention solves problems experienced with the priorart because it combines both quality and efficiency in the formingprocess. The present invention provides a dielectric layer and method ofmanufacture comprising a first layer dielectric having improved gap-fillat a low deposition rate as a first step, and an efficiently formedsecond dielectric layer as a second completing step.

[0012] Those and other advantages and benefits of the present inventionwill become apparent from the description of the preferred embodimentshereinbelow.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0013] For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein:

[0014]FIG. 1 is a cross-sectional view of a semiconductor of the presentinvention illustrating the dielectric layer of the present inventionformed over a substrate;

[0015]FIG. 2 is a cross-sectional view of an alternate embodiment of thedielectric layer of FIG. 1 formed over a gate electrode;

[0016]FIG. 3 is an alternate embodiment of the present inventionillustrating a top surface of the first dielectric layer positionedbelow an edge of the structure formed over the substrate;

[0017]FIG. 4 is an alternate embodiment of the present inventionillustrating a first dielectric layer formed below an edge of thestructure which is formed over the substrate so that a portion of theopening not filled by the first dielectric layer has an aspect ratio ofnot greater than two.

[0018]FIG. 5 illustrates the relationship between average void lengthand deposition temperature for 6.9% PSG at 200 torr;

[0019]FIG. 6 illustrates the relationship between average void lengthand deposition pressure for 6.9 PSG at 530° C.;

[0020]FIG. 7 illustrates the relationship between average void area andsuseptor spacing for 2.7×7.2 BPSG; and

[0021]FIG. 8 is a high level block diagram illustrating a systemutilizing the dielectric layer of the present invention.

[0022]FIG. 9 illustrates a prior art dielectric layer formation whereina sizable void is formed in the opening due to the shadowing effect.

DETAILED DESCRIPTION OF THE INVENTION

[0023] It is to be understood that the figures and descriptions of thepresent invention have been simplified to illustrate elements that arerelevant for a clear understanding of the present invention, whileeliminating, for purposes of clarity, other elements. Those of ordinaryskill in the art will recognize that other elements may be desirableand/or required in order to implement the present invention. However,because such elements are well known in the art, and because they do notfacilitate a better understanding of the present invention, a discussionof such elements is not provided herein.

[0024] The present invention will be described in terms of a dopedsilicon semiconductor substrate, although advantages of the presentinvention may be realized using other structures and technologies, suchas silicon-on-insulator, silicon-on-sapphire, and thin film transistor.The term substrate, as used herein, shall mean one or more layers orstructures which may include active or operable portions of asemiconductor device formed on or in the substrate. A substrate isoften, but not always, the lowest layer of material.

[0025]FIG. 1 is a cross-sectional view of an assembly 10 including anumber of structures 12 defining gaps or openings 18 formed on asubstrate 8 and covered with a multi-layer dielectric 2 including afirst dielectric layer 14 and a second dielectric layer 16. The assembly10 may be, for example, a portion of an integrated circuit, such as aportion of a memory array or a logic circuit, as may be used to formdevices, such as memories and processors.

[0026] The structures 12 are illustrated as being stepped structures,although they may take other forms. In the illustrated embodiment, thestructures 12 have edges 20 that define the opening 18. Although onlytwo openings 18 are illustrated in the drawings, any number of openings18 may be present on or in the substrate 8. The structures 12 may be,for example, conductive patterns formed directly on the substrate 8, andmay be formed, for example, from any conductor of current, such asaluminum and polysilicon. The structures 12 may be formed, for example,by a deposition and etch process. For example, a layer of aluminum maybe deposited over the entire substrate 8, such as by chemical vapordeposition (CVD) or by sputtering. The layer may be masked, such as withphotoresist, and subjected to a selective etch. Thereafter, thephotoresist may be removed to leave the structures 12 illustrated inFIG. 1.

[0027] The first dielectric layer 14 is formed with a relatively lowdeposition rate process and includes a top surface 15. The firstdielectric layer 14 may partially fill the opening 18 or may completelyfill the opening 18 and cover the edges 20. It has been discovered thatopenings 18 having aspect ratios greater than about two are difficult tofill at relatively high deposition rates and often suffer from shadowingeffects. As described hereinbelow, however, the method of forming thefirst dielectric layer 14 provides good gap-fill characteristics, evenat high aspect ratios of greater than about two. As a result, the firstdielectric layer 14 may partially fill the opening 18 so that theeffective aspect ratio of the opening 18 is less than about two, asillustrated in FIG. 4. The first dielectric layer 14 has desirablecharacteristics such as, for example, reducing “cross talk”, therebyincreasing reliability and performance. This benefit is realized whenthe opening 18 is completely or nearly completely filled, as illustratedin FIGS. 1 and 3, respectively.

[0028] The second dielectric layer 16 is formed with a higher depositionrate process than the first dielectric layer 14 to reduce processingtime, and includes a top surface 17 that is above the opening 18. Thesecond dielectric layer 16 may be formed at a higher deposition ratewithout producing undesirable gap-fill characteristics because the firstdielectric layer 14 has either completely filled the opening 18 or hasreduced the aspect ratio of the opening 18.

[0029] The first and second dielectric layers 14, 16 may be formed, forexample, from silicon oxide, tetraethylorthosilicate (TEOS) oxide,silicon nitride, or oxynitride. The first and second dielectric layers14, 16 may be formed, for example, through chemical vapor deposition(CVD) or sputtering. The relative deposition rates of the first andsecond dielectric layers 14, 16 may be controlled by changing one ormore process settings during the formation of the dielectric layers 14,16. The process settings include temperature, pressure, dopantconcentration, TEOS and dopant flow rates, and spacing between thesuseptor or shower head 28 and the assembly 10.

[0030] Several variables affect the gap-fill characteristics of thedielectric layer 2. For example, a deposition process using ozone andTEOS provides superior gap-fill properties over a process using hydrideprecursors such as silane and oxygen. It has been observed that someprocess conditions using ozone-TEOS deposition yield particularly goodgap-fill results. For example, undoped films provide better gap-fillcharacteristics and create less voids than doped films. Also, hightemperature and high pressure depositions provide better gap-fillcharacteristics than low temperature and low pressure depositions. Ingeneral, low deposition rate ozone-TEOS processes provide bettergap-fill than high deposition rate processes.

[0031] Controlling pressure to regulate deposition rates for the firstand second dielectric layers 14, 16 is particularly advantageous forpurposes of the present invention because pressure change can beaccomplished easily and quickly. Similarly, temperature may becontrolled to regulate deposition rates, such as with rapid thermalprocessing (RTP) techniques.

[0032] Changes in the process settings influence the deposition flowrate of the first dielectric layer 14 in order to reduce the aspectratio of the opening 18 to not greater than about two. The firstdielectric layer 14 may be formed at the following chemical processsettings in order to achieve low deposition rate: (1) a substratetemperature ranging from about 550° C. to about 600° C.; (2) a reactorchamber pressure ranging from about 400 torr to about 760 torr whenemploying TEOS; (3) a dopant concentration of boron ranging from about3% to about 5% by weight, preferably ranging from about 3% to about 4%by weight, and of phosphorus ranging from about 5% to about 8% byweight, preferably ranging from about 5% to about 6% by weight; (4) aTEOS flow rate from about 100 mg/min to about 300 mg/min; and (5) aspacing between the shower head 28 and the assembly 10 ranging fromabout 250 mil to about 300 mil. The first layer 14 may be formed, forexample, employing ozone-TEOS at a temperature of 575° C., a pressure of600 torr, a boron and phosphorus weight percent of 3% and 8%respectively, a flow rate of 300 mg/min, and a shower head spacing of275 mil. The first dielectric layer 14 may be formed at a depositionrate in the range of about 1,000 to about 2,000 Å/min when employingozone and tetraethylorthosilicate (TEOS).

[0033] The second dielectric layer 16 may be formed at the followingprocess settings in order to achieve high deposition rate: (1) asubstrate temperature ranging from about 400° C. to about 500° C.; (2) areactor chamber pressure ranging from about 100 torr to about 300 torrwhen employing TEOS; (3) a dopant concentration of boron ranging fromabout 3% to about 5% by weight, preferably ranging from about 4% toabout 5% by weight, and of phosphorus ranging from about 5% to about 8%by weight, preferably ranging from about 7% to about 8% by weight; (4) aTEOS flow rate from about 600 mg/min to about 700 mg/min; and (5) aspacing between the shower head 28 and the assembly 10 ranging fromabout 175 mil to about 200 mil. The second layer 16 may be formed, forexample, employing TEOS at a temperature of 480° C., a pressure of 200torr, a boron and phosphorus weight percent of 3% and 8% respectively, aflow rate of 600 mg/min, and a shower head spacing of 200 mil.Advantages of the present invention may be realized from a single changein a single process parameter or as a combination of changes in two ormore process parameters from the formation of the first dielectric layer14. The second dielectric layer 16 may be formed at a deposition rate inthe range of about 2,500 to about 4,000 Å/min. when employing ozone andTEOS.

[0034] Planarization may occur after formation of the first dielectriclayer 14, after formation of the second dielectric layer 16, or both.For example, mechanical abrasion, such as chemical-mechanicalplanarization (CMP), and reactive ion etch (RIE) etch-back planarizingare particularly useful in preparing the dielectric layer 2 of thepresent invention for subsequent processing steps.

[0035]FIG. 2 illustrates the assembly 10 in the form of a MOStransistor. The structures 12 a, 12 b, 12 c are contacts to source,gate, and drain portions, respectively, of the transistor 10. A gateoxide 22 is under the gate contact 12 b, and doped regions 24, 26 areformed in the substrate 8 under the source and drain contacts 12 a, 12c, respectively. The assembly 10 may also be used, for example, to formcapacitors and in memory arrays and logic arrays, such as may be used toform memory devices and processors.

[0036]FIG. 3 illustrates another embodiment of the present inventionwherein the top surface 15 of the first dielectric layer 14 is below thetop edge 20 of the structures 12, although still substantially fillingthe openings 18 therebetween. The second dielectric layer 16 is formedover and adjacent to the first dielectric layer 14. Although it isparticularly beneficial to form the first dielectric layer 14 that fillsthe openings 18 between the structures 12 so that its top surface 15completely covers the top edge 20, as described above, it iscontemplated that either by design or due to manufacturing variations,the top surface 15 of the first dielectric layer 14 may fall below theedges 20 of the structures 12 at various cross-sectional points alongthe top surface 15. In those situations, the first dielectric layer 14will still provide a high quality protective and insulating layerbetween the structures 12. The slight depressions 30 that fall below theedges 20 of the structures 12 would be covered and filled by the seconddielectric layer 16, and would not adversely effect the overallperformance of the dielectric layer 2. Furthermore, because the slightdepressions 30 have an aspect ratio of less than about two, they can beeffectively filled by the second dielectric layer 16.

[0037]FIG. 4 illustrates another embodiment of the present inventionwherein the top surface 15 of the first dielectric layer 14 issubstantially below the top edge 20 of the structures 12, so that theportion of the opening 18 not filled by the first dielectric layer 14has an aspect ratio greater than the slight depressions 30 illustratedin FIG. 3, but still not greater than about two. The first dielectriclayer 14 is formed at a low deposition rate that provides good surfacemobility that reduces or eliminates voids as a result of the shadowingeffect. The second dielectric layer 16 is formed over and adjacent tothe first dielectric layer 14 at a high deposition rate to complete theforming process. The second dielectric layer 14 may be formed quickly toreduce the manufacturing time and cost.

[0038] In operation, the present invention provides a dielectric layer 2comprising a first dielectric layer 14 formed at a low deposition rate,and a second dielectric layer 16 formed at a higher deposition rate. Thefirst dielectric layer 14 formed at the low deposition rate and processsetting ranges described above provide good gap-fill characteristicsduring the first step when the impingement rate is low so that voidsbetween the structures 12 due to the shadowing effect are eithereliminated or greatly reduced. As a result, the first dielectric layer14 provides improved protective, insulating and capacitive qualities inthe critical gap areas between the structures 12 where it is mostbeneficial, to protect the circuit from impurities, moisture, and stressrelated impacts. After the first dielectric layer is deposited using alow deposition rate process, and the spaces between the structure 12 areeither partially or completely filled, the second dielectric layer 16 isdeposited at a high deposition rate, thereby saving manufacturing timeand cost.

[0039] In addition, the present invention provides a method of formingthe multi-layer dielectric in openings 18 formed relative to thesubstrate 8. The first dielectric layer 14 is formed in an opening 18having an aspect ratio greater than about two at the relatively lowdeposition rate to substantially cover the openings 18 between thestructures 12 via the first set of process settings provided above. Thesecond dielectric layer 16 is then formed over and adjacent to the firstdielectric layer 14 at the relatively high deposition rate via thesecond set process settings provided above. The top surface 17 of thesecond dielectric layer 16 covers the opening 18 and completes theformation process.

[0040] The same method described above is used to form the dielectriclayer 2 illustrated in FIG. 3 but for the top surface 15 of the firstdielectric layer 14 being partially below the top edges 20 of thestructures 12 at various cross-sectional points along the top surface15. In like manner, the same method described above is used to form thedielectric layer 2 illustrated in FIG. 4, but the first dielectric layer14 is formed in an opening 18 having an aspect ratio greater than abouttwo so that a portion of the opening 18 not filled by the firstdielectric layer 14 has an aspect ratio not greater than about two.

[0041] Examples

[0042] The below examples are provided to show the relationship betweenvarious process conditions and void sizes measured in scanning electronmicroscope (SEM) cross-sections for phosphosilicate glass (PSG) andborophosphosilicate glass (BPSG) films deposited under a variety ofconditions. FIG. 5 shows the average void length versus depositiontemperature for 6.9% PSG at 200 torr. FIG. 6 shows the average voidlength versus deposition pressure for 6.9 PSG at 530° C. FIG. 7 showsthe average void area versus suseptor spacing for 2.7×7.2 BPSG. In eachof FIGS. 5-7, all other deposition parameters were held constant. FIGS.5-7 show that processes having lower deposition rates have bettergap-fill characteristics (smaller voids) than processes with higherdeposition rates.

[0043]FIG. 8 is a high level block diagram illustrating a system 50including a first device 52, a bus 54, and a second device 56. Thesystem 50 may be, for example, a memory system or a computer system. Thefirst device 52 may be a processor, and the second device 56 may be amemory. The first device 52 and the second device 56 may communicate viathe bus 54. The first and second devices 52, 56 may include assemblies,such as conductors, including dielectrics formed according to theteaching of the present invention, that may be used to form memoryarrays and logic circuits.

[0044] Those of ordinary skill in the art will recognize that manymodifications and variations of the present invention may beimplemented. The foregoing description and the following claims areintended to cover all such modifications and variations.

What is claimed is:
 1. A method of forming a dielectric layer in anopening, comprising: forming a first dielectric layer in the opening,the opening having an aspect ratio greater than about two, and wherein aportion of the opening not filled with said first dielectric layer hasan aspect ratio of not greater than about two; and forming a seconddielectric layer over the first dielectric layer, the second layerhaving a top surface that is not within the opening.
 2. The method ofclaim 1, further comprising providing a substrate before forming theopening.
 3. The method of claim 2, wherein providing the substrateincludes providing a substrate selected from the group consisting of asilicon substrate, an insulator substrate, and a sapphire substrate. 4.The method of claim 1, wherein forming a first dielectric layer includesforming the first dielectric layer having a top surface that is notwithin the opening.
 5. The method of claim 1, wherein forming a firstdielectric layer includes forming the first dielectric layer having atop surface that is within the opening.
 6. The method of claim 1,wherein: forming a first dielectric layer includes forming the firstdielectric layer through an ozone-TEOS deposition; and forming a seconddielectric layer includes forming the second dielectric layer through anozone-TEOS deposition.
 7. The method of claim 1, wherein: forming afirst dielectric layer includes forming the first dielectric layer at afirst process setting; and forming a second dielectric layer includesforming the second dielectric layer at a second process setting at apredetermined relationship with the first process setting.
 8. The methodof claim 7, wherein the first process setting and the second processsetting are selected from the group consisting of temperature, reactorchamber pressure, dopant concentration, flow rate, and shower headspacing.
 9. The method of claim 1, wherein: forming a first dielectriclayer includes forming the first dielectric layer at a firsttemperature; and forming a second dielectric layer includes forming thesecond layer at a second temperature, the second temperature being lessthan the first temperature.
 10. The method of claim 1, wherein: forminga first dielectric layer includes forming the first dielectric layer ata first pressure; and forming a second dielectric layer includes formingthe second dielectric layer at a second pressure, the second pressurebeing greater than the first pressure.
 11. The method of claim 1,wherein: forming a first dielectric layer includes forming the firstdielectric layer at a first dopant concentration; and forming a seconddielectric layer includes forming the second layer at a second dopantconcentration, the first dopant concentration being less than the seconddopant concentration.
 12. The method of claim 1, wherein: forming afirst dielectric layer includes forming the first dielectric layer at afirst total TEOS and dopant flow rate; and forming a second dielectriclayer includes forming the second layer at a second total TEOS anddopant flow rate, the first total TEOS and dopant flow rate being lessthan the second total TEOS and dopant flow rate.
 13. The method of claim1, wherein: forming a first dielectric layer includes: providing ashower head at a first distance from the substrate, and providingthrough the shower head constituents forming the first layer; andforming the second dielectric layer includes: providing the shower headat a second distance from the substrate, the second distance lower thanthe first distance, and providing through the shower head constituentsforming the second layer.
 14. A method of forming a dielectric layerduring the manufacture of a semiconductor device, comprising: providinga substrate; forming an opening relative to the substrate, the openinghaving an aspect ratio greater than about two; forming a firstdielectric layer in the opening wherein a portion of the opening notfilled with said first dielectric layer has an aspect ratio of notgreater than about two; and forming a second dielectric layer over thefirst dielectric layer, the second layer having a top surface that isnot within the opening.
 15. The method of claim 14, wherein forming anopening includes forming an opening in the substrate.
 16. The method ofclaim 14, wherein forming an opening includes forming an opening on thesubstrate.
 17. The method of claim 14, wherein forming an openingincludes forming a plurality of structures on the substrate so that saidplurality of structures forms an opening.
 18. The method of claim 17,wherein forming a plurality the structures includes forming a pluralityof conductors.
 19. A method of forming a dielectric layer in an opening,comprising: forming a first dielectric layer in the opening, the firstlayer having a first process setting; and forming a second dielectriclayer over the first dielectric layer, the second layer having a topsurface that is not within the opening and having a second processsetting at a predetermined relationship with the first process setting.20. The method of claim 19, wherein the first process setting and thesecond process setting are selected from the group consisting oftemperature, reactor chamber pressure, dopant concentration, flow rate,and shower head spacing.
 21. The method of claim 19, wherein the firstprocess setting includes a first temperature, and the second processsetting includes a second temperature, the first temperature beinggreater than the second temperature.
 22. The method of claim 19, whereinthe first process setting includes a first pressure, and the secondprocess setting includes a second pressure, the first pressure beinggreater than the second pressure.
 23. The method of claim 19, whereinthe first process setting includes a first dopant concentration, and thesecond process setting includes a second dopant concentration, the firstdopant concentration being less than the second dopant concentration.24. The method of claim 19, wherein the first process setting includes afirst flow rate, and the second process setting includes a second flowrate, the first flow rate being less than the second flow rate.
 25. Themethod of claim 19, wherein the first process setting includes:providing a shower head at a first distance from the substrate, andproviding through the shower head constituents forming the first layer;and said second process setting includes: providing the shower head at asecond distance from the substrate, the second distance lower than thefirst distance, and providing through the shower head constituentsforming the second layer.
 26. A method of forming a dielectric layer inan opening, comprising: forming a first dielectric layer completelyfilling the opening, the opening having an aspect ratio greater thanabout two; and forming a second dielectric layer over the firstdielectric layer.
 27. A method of forming a dielectric layer in anopening, comprising: forming a first dielectric layer in the opening,the first layer being formed at a first temperature; and forming asecond dielectric layer over the first dielectric layer, the secondlayer having a top surface that is not within the opening and beingformed at a second temperature, the first temperature being greater thanthe second temperature.
 28. A method of forming a dielectric layer in anopening, comprising: forming a first dielectric layer in the opening,the first layer being formed at a first pressure; and forming a seconddielectric layer over the first dielectric layer, the second layerhaving a top surface that is not within the opening and being formed ata second pressure, the first pressure being greater than the secondpressure.
 29. A method of forming a dielectric layer in an opening,comprising: forming a first dielectric layer in the opening, the firstlayer having a first dopant concentration; and forming a seconddielectric layer over the first dielectric layer, the second layerhaving a top surface that is not within the opening and having a seconddopant concentration, the first dopant concentration being less than thesecond dopant concentration.
 30. A method of forming a dielectric layerin an opening, comprising: forming a first dielectric layer in theopening, the first layer being formed at a first flow rate; and forminga second dielectric layer over the first dielectric layer, the secondlayer having a top surface that is not within the opening and beingformed at a second flow rate, the first flow rate being less than thesecond rate.
 31. A method of forming a dielectric layer in an opening,comprising: forming a first dielectric layer in the opening, saidforming the first layer including: providing a shower head at a firstdistance from the substrate, and providing through the shower headconstituents forming the first layer; and forming a second dielectriclayer over the first dielectric layer, the second layer having a topsurface that is not within the opening, said forming the second layerincluding: providing the shower head at a second distance from thesubstrate, the second distance lower than the first distance, andproviding through the shower head constituents forming the second layer.32. An assembly, comprising: a substrate; an opening relative to saidsubstrate, said opening having an aspect ratio greater than about two; afirst dielectric layer in said opening wherein a portion of said openingnot filled with said first dielectric layer has an aspect ratio of notgreater than about two; and a second dielectric layer over said firstdielectric layer, said second layer having a top surface that is notwithin said opening.
 33. The assembly of claim 32, wherein said openingis formed from a plurality of structures on said substrate.
 34. Theassembly of claim 32, wherein said first dielectric layer is selectedfrom a group consisting of silicon oxide, TEOS oxide, silicon nitrideand oxynitride.
 35. The assembly of claim 32, wherein said seconddielectric layer is selected from a group consisting of silicon oxide,TEOS oxide, silicon nitride and oxynitride.
 36. The assembly of claim32, wherein said first layer includes a top surface that is within saidopening.
 37. The assembly of claim 32, wherein said first layer includesa top surface that is not within said opening.
 38. The assembly of claim32, wherein said assembly forms a portion of a device selected from agroup consisting of a transistor, a capacitor, a logic circuit, a memoryarray, a memory device, and a processor.
 39. An assembly, comprising: aplurality of structures forming an opening, said opening having anaspect ratio greater than about two; a first dielectric layer in saidopening wherein a portion of said opening not filled with said firstdielectric layer has an aspect ratio of not greater than about two; anda second dielectric layer over said first dielectric layer, said secondlayer having a top surface that is not within said opening.
 40. Theassembly of claim 39, wherein said plurality of structures areconductors.
 41. The assembly of claim 40, wherein said plurality ofstructures are selected from a group consisting of aluminum andpolysilicon.
 42. The assembly of claim 39, wherein said plurality ofstructures are parallel conductors.
 43. The assembly of claim 39,wherein said plurality of structures are stepped structures.
 44. Theassembly of claim 39, wherein said plurality of structures includesidewalls defining said opening.
 45. The assembly of claim 39, whereinsaid assembly forms a portion of a device selected from a groupconsisting of a transistor, a capacitor, a logic circuit, a memoryarray, a memory device, and a processor.
 46. The assembly of claim 39,wherein said plurality of conductors are formed on a substrate.
 47. Anassembly, comprising: a plurality of conductors forming an opening, saidopening having an aspect ratio greater than about two; a firstdielectric layer in said opening wherein a portion of said opening notfilled with said first dielectric layer has an aspect ratio of notgreater than about two ; and a second dielectric layer over said firstdielectric layer, said second layer having a top surface that is notwithin said opening.
 48. The assembly of claim 47, wherein saidconductors are parallel conductors.
 49. An assembly, comprising: asubstrate; an opening relative to said substrate, said opening havingan, aspect ratio greater than about two; a first ozone-TEOS layer insaid opening wherein a portion of said opening not filled with saidfirst dielectric layer has an aspect ratio of not greater than abouttwo; and a second ozone-TEOS layer over said first layer, said secondlayer having a top surface that is not within said opening.
 50. Anassembly, comprising: a plurality of structures forming an opening, saidopening having an aspect ratio greater than about two; a firstozone-TEOS layer in said opening wherein a portion of said opening notfilled with said first dielectric layer has an aspect ratio of notgreater than about two; and a second ozone-TEOS layer over said firstlayer, said second layer having a top surface that is not within saidopening.
 51. A system, comprising: a first device including a substrate,an opening relative to said substrate, said opening having an aspectratio greater than about two, a first dielectric layer in said openingwherein a portion of said opening not filled with said first dielectriclayer has an aspect ratio of not greater than about two, a seconddielectric layer over said first dielectric layer, said second layerhaving a top surface that is not within said opening; a second device;and a bus connected to both said first device and said second device.52. The system of claim 51, wherein said first device is selected from agroup consisting of a transistor, a capacitor, a logic circuit, a memoryarray, a memory device, and a processor.
 53. The system of claim 51,wherein said first device is a memory device and said second device is amemory device.
 54. A system, comprising: a first device including aplurality of structures forming an opening, said opening having anaspect ratio greater than about two, a first dielectric layer in saidopening wherein a portion of said opening not filled with said firstdielectric layer has an aspect ratio of not greater than about two, anda second dielectric layer over said first dielectric layer, said secondlayer having a top surface that is not within said opening; a seconddevice; and a bus connected to both said first device and said seconddevice.
 55. The system of claim 54, wherein said first device isselected from a group consisting of a transistor, a capacitor, a logiccircuit, a memory array, a memory device, and a processor.
 56. Thesystem of claim 54, wherein said first device is a memory device andsaid second device is a memory device.
 57. The system of claim 54,wherein said plurality of structures in said first device are formed ona substrate.